1. Field of the Invention
The present invention relates to a data hold circuit capable of achieving power-saving of a logic circuit by holding the state of a node or nodes in the logic circuit.
2. Description of Related Art
Power management technique for saving power of a circuit has been used recently. To save power, a clock frequency of a circuit in an non-operation state is decreased, or the power supply to the circuit is interrupted. Such a circuit is generally arranged using a static circuit. Here, a static circuit is a term representing the opposite of a dynamic circuit, and refers to a circuit which holds a logic state by a constant current or voltage. On the other hand, a dynamic circuit refers to a circuit which utilizes a temporary storing function of the capacitance of a MOS transistor. Although a static circuit employs a power-saving technique which interrupts a clock signal while maintaining the power in the ON state, it is unavoidable for a current to flow to some extent.
Thus, a more promising power management technique is thought, in which the power supply to a non-operating block of a circuit, or to a non-operating circuit in its entirety, is turned off. This technique, however, is seldom used at present. This is because a circuit such as a flip-flop cannot hold its state when the power supply is turned off in spite of its necessity to hold its state during a non-operation state. Accordingly, a high speed circuit is desired which can hold its state even if the power supply is turned off.